(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of simultaneously reading data and refreshing data.
(2) Description of the Related Art
Since DRAMs (Dynamic Random-Access Memories) are required to refresh memory cells, it has heretofore been customary to temporarily inhibit access from an external circuit while refreshing memory cells.
Temporary inhibition of access to a DRAM from an external circuit poses a disadvantage on the DRAM especially when there is a demand for high-speed access because the response time for access is prolonged by the temporary inhibition.
In view of the above drawback, the applicant filed a patent application on an invention relating to a semiconductor memory device (hereinafter referred to as “semiconductor memory device disclosed in a filed application”) that can be accessed from an external circuit even while its memory cells are being refreshed (Japanese patent application No. 2000-368423).
FIG. 11 of the accompanying drawings is a diagram illustrative of the principles of operation of the semiconductor memory device disclosed in the filed application. As shown in FIG. 11, the semiconductor memory device disclosed in the filed application comprises a memory array of 16 subblocks and a parity array of 4 subblocks.
Each of the subblocks comprises a cell array in the form of a matrix of memory cells, a sense amplifier, and a decoder.
The subblocks of the memory array serve to store ordinary data, and the subblocks of the parity array serve to store parity data.
FIG. 12 of the accompanying drawings is a diagram illustrative of the manner in which data are read from the memory array. As shown in FIG. 12, when data are to be read from the memory array, data D1 through D4 are read from a row of subblocks (shown shaded).
FIG. 13 of the accompanying drawings is a diagram illustrative of the manner in which memory cells are refreshed. In the semiconductor memory device disclosed in the filed application, the subblocks are successively refreshed one at a time. In the example shown in FIG. 13, a subblock 2-3 shown hatched is to be refreshed. According to a specific example of operation, the subblocks of one row are refreshed successively from the left to the right. When all the subblocks of one row have been refreshed, then the subblocks of a next row start to be refreshed.
FIG. 14 of the accompanying drawings is a diagram illustrative of the manner in which subblocks are refreshed and data are read concurrently, with subblocks to be refreshed and subblocks to read data from overlapping each other.
In the example shown in FIG. 14, data are to be read from subblocks 2-1 through 2-4 of the memory array, and data in subblock 2-3 of the memory array are to be refreshed.
In this case, since the data cannot be read from the subblock 2-3, the semiconductor memory device disclosed in the filed application supplies data output from the subblocks 2-1, 2—2, 2-4 and parity data read from a subblock 2P to a data restoring circuit 200, which restores the data of the subblock 2-3 from the supplied data.
FIG. 15 is a block diagram of a detailed arrangement of the semiconductor memory device disclosed in the filed application.
As shown in FIG. 15, the semiconductor memory device disclosed in the filed application comprises an XOR circuit 10, a parity cell 11, DQ0 through DQ3 cells 12 through 15, an XOR circuit 16, a refresh signal generating circuit 17, and selectors 18 through 21.
The XOR circuit 10 XORs data DQ0 through DQ3 input thereto, and writes the result as parity data in the parity cell 11.
The DQ0 through DQ3 cells 12 through 15 store data input thereto, and supply data read according to a readout request to the selectors 18 through 21.
The refresh signal generating circuit 17 generates refresh signals for refreshing the DQ0 through DQ3 cells 12 through 15, and supplies the generated refresh signals to the selectors 18 through 21. In the illustrated example, the DQ0 cell 12 is shown hatched and is being refreshed. Therefore, only the refresh signal output from the refresh signal generating circuit 17 to the selector 18 is “H” (high in level), and the other refresh signals output from the refresh signal generating circuit 17 to the selectors 19 through 21 are “L” (low in level).
If both the output signal from the XOR circuit 16 and the output signal from the refresh signal generating circuit 17 are “H”, then the selectors 18 through 21 select and output signals which are an inversion of the output signals from the DQ0 through DQ3 cells 12 through 15. Otherwise, the selectors 18 through 21 directly output the output signals from the DQ0 through DQ3 cells 12 through 15.
FIG. 16 is a block diagram of a detailed arrangement of the selectors 18 through 21.
As shown in FIG. 16, each of the selectors 18 through 21 comprises a NAND element 30, inverters 31, 32, and transfer circuits 33, 34.
The NAND element 30 supplies an inversion of the logical product of the output signal (hereinafter referred to as “refresh signal”) from the refresh signal generating circuit 17 and the output signal (hereinafter referred to as “XOR signal”) from the XOR circuit 16, to the inverter 31, an inverting input terminal of the transfer circuit 33, and a non-inverting input terminal of the transfer circuit 34.
The inverter 31 supplies the inversion of the output signal from the NAND element 30 to a non-inverting input terminal of the transfer circuit 33 and an inverting input terminal of the transfer circuit 34.
The inverter 32 supplies an inversion of the output signal from the corresponding cell, which is either one of the DQ0 through DQ3 cells 12 through 15, to the transfer circuit 33.
If the output signal from the NAND element 30 is “L”, then the transfer circuit 33 directly outputs the signal from the inverter 32.
If the output signal from the NAND element 30 is “H”, then the transfer circuit 34 directly outputs the cell data.
Operation of the semiconductor memory device disclosed in the filed application will be described below.
When the input data DQ0 through DQ3 are supplied, the XOR circuit 10 XORs the supplied data, and supplies the result to the parity cell 11. The parity cell 11 stores the output signal from the XOR circuit 10 as parity data.
The DQ0 through DQ3 cells 12 through 15 store the input data DQ0 through DQ3, respectively. Since input data DQ0 through DQ3 are all “1” in this example, the DQ0 through DQ3 cells 12 through 15 store “1”, and the parity cell 11 stores “0” which is the exclusive OR of input data DQ0 through DQ3.
When there is a request for reading data at this time, the data are read from the DQ0 through DQ3 cells 12 through 15 and the parity cell 11. If the DQ0 cell 12 is to be refreshed at this time, then since the data cannot properly be read from the DQ0 cell 12, any data read therefrom are undefined (?).
The XOR circuit 16 XORs the data read from the DQ0 through DQ3 cells 12 through 15 and the parity data read from the parity cell 11, and supplies the exclusive OR as an XOR signal to the selectors 18 through 21. The XOR signal is “H” if the data written in the DQ0 through DQ3 cells 12 through 15 and the data read from the DQ0 through DQ3 cells 12 through 15 do no agree with each other, and is “L” otherwise. Therefore, the XOR signal which is “H” represents an error.
In this example, the data DQ0 is undefined. If the data DQ0 is “1”, then the data written in the DQ0 through DQ3 cells 12 through 15 and the data read from the DQ0 through DQ3 cells 12 through 15 agree with each other, and hence the XOR signal is “L”. If the data DQ0 is “0”, then the data written in the DQ0 through DQ3 cells 12 through 15 and the data read from the DQ0 through DQ3 cells 12 through 15 do not agree with each other, and hence the XOR signal is “H”.
If the XOR signal is “H”, then since the signal supplied from the refresh signal generating circuit 17 to the selector 18 is “H”, the output signal from the NAND element 30 is “L”. As a result, the transfer circuit 33 is turned ON, outputting a signal “1” which is an inversion of the input DQ0 which is “0”. Because the output signal “1” is the same as the input DQ0, the data is properly restored.
If the output signal from the DQ0 cell 12 is “1”, then since the XOR signal is “L”, the output signal from the NAND element 30 is “H”. As a result, the transfer circuit 34 is turned ON, directly outputting the input DQ0.
Since the output signals supplied from the refresh signal generating circuit 17 to the selectors 19 through 21 are “L”, the output signals from the NAND elements 30 of the respective selectors 19 through 21 are “H”, turning ON the transfer circuit 34. The transfer circuit 34 thus directly outputs the data read from the DQ1 through DQ3 cells 13 through 15.
As described above, even when the semiconductor memory device disclosed in the filed application operates simultaneously in a refresh mode and a readout mode, the data stored in the cell that is being refreshed is restored from the parity data stored in the parity cell 11 and the other data. Therefore, the refresh mode and the readout mode can be carried out concurrently with each other, resulting in an increase in the access speed.
The semiconductor memory device disclosed in the filed application is disadvantageous in that since the parity data stored in the parity cell 11 cannot directly be read and written, it is difficult to determine whether the parity cell 11 and the function associated therewith, i.e., the data restoring function, are normal or not.
The semiconductor memory device disclosed in the filed application is also problematic in that when the data stored in the DQ0 through DQ3 cells 12 through 15 are to be read, since the data are subject to a restoring process based on the parity data depending on the refreshing operation, the stored data cannot directly be read, making it difficult to perform an operation check.